The inventive concept relates to non-volatile memory devices, and more particularly, to non-volatile memory devices having reduced programming periods while maintaining acceptable bit error rates (BER). The inventive concept also relates to methods of programming such non-volatile memory devices.
In certain conventional nonvolatile memory devices, such as flash memory, data is stored by defining the threshold voltage of a constituent memory cell. The definition (or adjusting) of a memory cell threshold voltage such that it falls within one of a number of defined threshold voltage distributions may be accomplished using a variety of programming methods. For example, in one class of programming methods, a sequence of high-voltage pulses having variable levels (e.g., sequentially increasing) is applied to the control gate of the memory cell in order to adjust its threshold voltage. Such programming methods are commonly referred to as “incremental-step pulse programming” or “ISPP”.
Due to demands for greater data density, that is commercial pressure to store increasingly large amounts of data using smaller physical areas, certain conventional memory devices now make use of so-called “multi-level memory cells” (MLC) that are capable of storing two or more data bits per memory cell. However, while this approach is effective in providing increased data density, there are challenges involved in the programming of MLC. For example, adjacent memory cells coupling effects during multi-bit programming has an increased propensity to “disturb” (i.e., inadvertently change) data that has been previous programmed to a MLC.
Such coupling effects between adjacent (or proximate) memory cells may generally be reduced by the programming approaches that use a number of programming steps. However, the use of more programming steps to avoid coupling effects, increases the time required to program (i.e., the “programming period”) the MLC. As has been conventionally determined, the number of programming steps used to program MLC may be reduced by the use of a so-called “pre-equalization programming techniques.” Those skilled in the art understand that certain pre-equalization programming approaches essentially pre-compensate the threshold voltage of a memory cells during a programming operation in view of additional programming operations that will be applied to an adjacent (or proximate) memory cell.
Nonetheless, while certain conventional ISPP methods may be improved in their application by the use of pre-equalization programming techniques, the use of such pre-equalization programming techniques tends to drive up the number of verification voltages that must be used during program verification operations. This increased number of verification voltages and their application during program verification operations also inevitably increases the programming period associated with a programming operation.